룰렛 배팅

Overview

This chip can transmit 39bits video data and 3bit control signal via only a single differential cable at an LVDS clock frequency form 20MHz to 100MHz

  • LVDS to V-by-One®
  • 6ch LVDS 2port(Dual Pixel Link) 입력
    　36bits/pixel
    　140-700Mbps/ch
  • HS 2lanes output
    75Gbps(effective rate 3
  • Power Supply: 1
  • Package: TSSOP64
  • Recommended Rx:
    　룰렛 배팅16
    　룰렛 배팅18
LVDS 데이터 입력 V-by-One® Input Clock Frequency
4ch (24bit) 1Lane 20MHz ~ 100MHz
4ch (24bit) x2 2Lane 20MHz ~ 100MHz
5ch (30bit) 1Lane 20MHz ~ 85MHz
5ch (30bit) x2 2Lane 20MHz ~ 85MHz
6ch (36bit) 1Lane 20MHz ~ 75MHz
6ch (36bit) x2 2Lane 20MHz ~ 75MHz

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FAQ

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